The escalating requirements for density and performance associated with ultra large scale integration (ULSI) circuits require responsive changes in interconnection technology which is considered a very demanding aspect of ULSI technology. High density demands for ULSI integration require planarizing layers with minimal spacing between conductive lines.
Single damascene is a technique developed to address disadvantages (e.g., poor metal step coverage, residual metal shorts, low yields, uncertain reliability, and poor ULSI integration extendability) associated with traditional etch back methods. Damascene, an art which has been employed for centuries in the fabrication of jewelry, has been adapted for application in the semiconductor industry. Damascene basically involves the formation of a trench which is filled with a metal. Thus, damascene differs from traditional etch back methods which involve building up a metal wiring layer and filling the interwiring spaces with a dielectric material.
Single damascene techniques offer the advantage of improved planarization as compared to etch back methods; however, single damascene is time consuming in that numerous process steps are required. Undesirably, an interface exists between the conductive via and conductive wiring. Moreover, adequate planarization layers containing an interwiring spacing less than 0.35 .mu.m are difficult to achieve.
An improvement to single damascene is dual damascene which involves substantially simultaneous formation of a conductive via and conductive wiring. The dual damascene technique requires less manipulative steps than the single damascene technique and eliminates the interface between the conductive via and conductive wiring which is typically formed by the single damascene technique. In very and ultra large scale integration (VLSI and ULSI) circuits, an insulating or dielectric material, such as silicon oxide, of the semiconductor device in the dual damascene process is patterned with several thousand openings for the conductive lines and vias which are filled with metal, such as aluminum, and serve to interconnect active and/or passive elements of the integrated circuit. The dual damascene process also is used for forming multilevel signal lines of metal, such as copper, in the insulating layers, such as polyimide, of multilayer substrate on which semiconductor devices are mounted.
A conventional dual damascene process is illustrated in FIGS. 1a-1h in connection with a semiconductor structure 18. FIG. 1a illustrates an insulative layer 20 formed on a semiconductor substrate (not shown). A photoresist layer 22a is formed on the insulative layer 20. The photoresist layer 22a is patterned using conventional techniques to form a first opening 30 (FIG. 1b). Anisotropic reactive ion etching (RIE) is performed to form a via 40 (FIG. 1c) in the insulative layer 20. Subsequently, a second layer of photoresist 22b (FIG. 1d) is formed over the structure 18.
The second photoresist layer 22b is patterned to form a second opening 48 (FIG. 1e) about the size of the ultimate trench. Anisotropic RIE is again performed to form a trench 50 (FIG. 1f) in the insulative layer 20. Although this standard dual damascene technique offers advantages over other processes for forming interconnections, it has a number of disadvantages, such as the edges of the via openings and the sidewalls of the via 40 in the lower half of the insulating layer 20 are poorly defined because of the two etchings and the via edges and sidewalls being unprotected during the second etching. More particularly, gases from the second etch step leak under photoresist portion 22c and damage edges and sidewalls of the via 40 as illustrated in FIGS. 1g and 1h.
In view of the above, improvements are needed to mitigate poor edge and sidewall definition of vias associated with conventional dual damascene processes.